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Limited specifications of Advanced Micro Devices' forthcoming Hammer technology were revealed at the Hot Chips conference at Stanford University in California on Wednesday, including the clock speed and die size of the Athlon version of the Hammer chips, according to an analyst report. However, AMD is denying the accuracy of the information distributed by the analyst.

The desktop Athlon chip, code-named Clawhammer, is expected to run at 2.5 GHz to start, says Joe Osha, an analyst with Merrill Lynch who attended the conference, in a research note distributed Thursday. Osha later said that he deduced the clock speed from information he got at the conference from his own sources and available materials, and that the speed was not revealed by AMD.

Though that speed is less than the clock speeds of chips from Intel due out Monday and later this year, AMD says its chips are based on a more efficient architecture and can execute more instructions per clock cycle than Intel's.

Speed Limits

However, AMD's rating system for its current, seventh-generation Athlon chips might have to be reworked if the reported 2.5-GHz clock speed is correct. The system uses internal benchmarks to rate the performance of Athlon chips compared with competing chips. For instance, the Athlon XP 2600+, released Wednesday, runs at 2.133 GHz but is said to perform as well as or better than Intel's top-end 2.53-GHz Pentium 4.

A 2.5-GHz Hammer chip would need to conform to a different ratings structure because its performance is likely to be well beyond that of the Athlon XP 2600+.

AMD "has certainly not set guidance for the Hammer. [AMD CEO] Jerry Sanders has talked about entering around 2 GHz, but we haven't set the clock speed officially, or the model number," says John Crank, AMD brand manager.

AMD revealed this week that it is working with PC vendors to develop a rating system for PCs that takes into account factors other than the clock speed of a PC's processor. The rating system will be released as soon as the company determines a reliable performance metric, AMD says. The Athlon version of the Hammer technology is scheduled to be available near the end of this year.

Sizable Issues

AMD, based in Sunnyvale, California, has also managed to limit the increase in die size--or the surface area occupied by a chip--to only 2 percent or 3 percent compared with similar x86-based chips, according to Osha's research note. This small increase in die size applies only to 32-bit chips that are turned into 64-bit processors without any additional enhancements, Crank says.

Osha said later that the server version of the Hammer technology, the Opteron chip, would not fall into that category, as it includes three HyperTransport nodes and uses on-chip memory. This would increase the die size by more than 3 percent, he added.

Smaller die sizes increase the number of chips that a chip maker can produce per silicon wafer, says Shane Rau, a senior research analyst at IDC in Mountain View, California. The more chips produced per silicon wafer, the lower the cost of each individual chip to end users, Rau says.

AMD has not disclosed officially the die sizes of the Hammer technology, but will do so when the product is launched, Crank says.

Osha says that the the Opteron chip will compete with Intel's Xeon server chips, not with Intel's Itanium chips. Itanium chips boast performance superior to that of other x86-based server chips, but they are expensive and have had difficulty breaking into the high-end server market dominated by RISC (reduced instruction set computing) chips from Sun Microsystems and IBM, among others. By pricing the Opteron relative to the more profitable Xeon chip, AMD will attempt to make inroads into the low- and midrange server market, Osha says.

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