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Supercomputer-on-Chip in the Works

IBM, University of Texas team on new technique to support 1 trillion operations per second.

Tom Krazit, IDG News Service

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A new chip under development by IBM and the University of Texas at Austin might produce supercomputer-like performance reaching 1 trillion operations per second by the end of the decade, IBM says.

The new TRIPS (tera-op reliable intelligently adaptive processing system) architecture developed by researchers uses a technique called block-oriented execution. This allows the chip to process large chunks of information in parallel, rather than waiting for a sequence of instructions to finish before taking on the next batch.

Hefty Goals

The joint project will attempt to develop a processor with the TRIPS architecture and up to four processor cores, IBM says. That chip is expected to contain 250 million transistors and run at 500 MHz, according to IBM representatives.

The shared project by IBM and the University of Texas is intended to show that a processor with the TRIPS architecture can scale up to 10 GHz, reaching the goal of 1 trillion operations per second. Modern supercomputers can process several trillion operations per second, but require hundreds or thousands of processors to reach those numbers.

Professors at the University of Texas say they hope to develop prototype chips by the end of 2005. IBM Microelectronics is expected to take over volume production once the chips are ready, IBM says.

Other Efforts

Multicore designs are considered the future of supercomputer and server processors. IBM's Power4 already incorporates a dual-core design.

Several other prominent vendors are also planning multicore processors.

Sun Microsystems showed its work in progress at a meeting earlier this year. Also, Intel is developing a multicore Itanium system. And Hewlett-Packard has expressed plans to produce multicore processor systems.

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