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By combining two semiconductor manufacturing techniques, IBM will boost transistor performance by about 50 percent in the next three to five years, the company says.

The two techniques, strained silicon and silicon on insulator (SOI), have been brought together for the first time in a technique called strained silicon directly on insulator (SSDOI), IBM says. Also, IBM has developed another way to increase transistor performance by combining different substrates on a single wafer, says Meikei Ieong, senior manager of exploratory device and integration at IBM Research.

Power Capture

To keep increasing the speed of current flowing through a chip, designers find different ways to reduce power leakage and increase the mobility of electrons within a circuit. One current technique is SOI, which adds a thin oxide layer to a silicon wafer in order to insulate the circuit against power leakage.

Advanced Micro Devices uses this technique in its Opteron server processor, and IBM has also used the technique.

Strained silicon, which is expected to appear on Intel's 90-nanometer chips, involves depositing a layer of silicon germanium on top of a silicon wafer. This stretches the silicon atoms to let electrons flow faster through a circuit.

IBM's new research enables the company to use a layer transfer technique to apply both SOI and strained silicon to the same silicon wafer, Ieong says.

Researchers create a layer of strained silicon on top of a layer of silicon germanium, and then add an oxide layer atop that structure. That structure is flipped over and placed on top of a second silicon wafer. This allows researchers to remove the layer of silicon germanium at the end of the process, Ieong says.

By removing that layer of silicon germanium, IBM can improve the thermal conductivity of the wafer. It also eliminates a foreign material from the manufacturing process that adds complexity, he says.

This technique won't be ready for production chips for another three to five years, Ieong says. It might make its debut on IBM's 65nm process technology, he adds.

Mixed Methods

IBM's other new manufacturing technique mixes the surface orientations favored by different types of transistors on a single wafer, Ieong says.

Traditionally, chip makers have manufactured silicon wafers that favor only negatively charged transistors. Designers had to choose whether to optimize their substrates for negatively charged transistors or positively charged ones. Since they could get better overall performance out of a wafer optimized for a negatively charged transistor, that's the way the chips were manufactured.

So in every chip, the negative transistors ran at optimal performance, but the positive transistors were not optimized. IBM has now developed a way to layer the substrate material that favors the positive transistors below the surface of the wafer that favors the negative transistors, Ieong says. IBM then punches holes in the surface to bring the positive transistor substrate to the surface of the wafer, Ieong says.

This means the wafer surface has a mixed orientation that favors both positive and negative transistors, improving overall chip performance by between 40 percent and 65 percent, Ieong says. This technique could be implemented on IBM's 90nm process technology, but probably won't be ready for full production volumes for another three to five years, he adds.

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