SAN FRANCISCO -- The "tera" era of the computing world is approaching, and the semiconductor industry will have to rethink many of its architectural approaches in order to handle the vast datasets of the future, says Pat Gelsinger, senior vice president and chief technology officer at Intel.
As is traditional, Gelsinger took the last day of the biannual Intel Developer Forum here to describe the chip maker's plans for new technologies and products in the coming five to ten years. In the past, he has talked up everything from software-defined radios to biosensor networks, but this year he focused on Intel's fundamental role as a chip architect.
"We're at the tip of the iceberg in terms of the digitization of information," Gelsinger said in his Thursday afternoon address. As more information is recorded digitally, processors will need to handle terabytes of data and deliver terabits per second of bandwidth, he said. One terabyte is equal to one trillion bytes, or 1024 gigabytes.
In order to handle that much data, computers will need to adapt, search large amounts of data for relevant information, and reach a conclusion based on the whole process, Gelsinger said. Performance will increase through shrinking transistors and other innovations, but he believes an architectural change is necessary to handle the tera era.
Not just processing power must increase in order to reach those goals, Gelsinger added. Memory, interconnects, and storage will all need to scale alongside processing power in order to realize this vision of the future.
One way Intel is working toward the tera era is by using architectural techniques such as helper threads. Helper threads increase the performance of single-threaded applications by executing as many tasks as possible in parallel on a single processor. This technique becomes even more effective as multicore processors roll out, Gelsinger said. Multicore processors integrate more than one CPU onto a single chip.
Another method is the use of software-defined radios to let users quickly switch between wireless connections to communicate as effectively as possible, Gelsinger said.
This vision of the tera era won't likely appear before the end of the decade, but the industry needs to prepare, Gelsinger said.
Before Gelsinger's talk, Intel Executive Vice President and General Manager Sean Maloney offered an update on Intel's communications business. This effort endured a difficult year in 2003, with Intel writing off $600 million in goodwill after realizing in December the communications business wouldn't grow as fast as expected. The flash memory and applications processor business was folded into Maloney's wired and wireless networking group late last year.
Maloney announced a 90-nanometer flash memory product during his first keynote as head of the combined Intel Communications Group. This will be the first NOR flash memory product released at 90 nanometers, according to Intel. (NOR is the type of memory commonly used in cell phones.) The company expects to release samples with densities of 64 megabits in April, and start volume production in the third quarter.
Intel also updated its vision for WiMax, the metro-area wireless networking standard that the company thinks will help solve the "last-mile" problem of broadband penetration. Only Japan and South Korea have more than 50 percent of their households using high-speed connections to get on the Internet, and WiMax could help increase that number, Maloney said.
Wired broadband connections are costly to install and maintain, but Intel expects WiMax will jump over all those hurdles. Maloney says the first WiMax products will roll out over the course of 2004.
Consumers should be able to install an antenna on their homes that can access WiMax signals during the first half of 2005, Maloney said. He expects the technology will advance to the point that connections are possible without an antenna by the end of 2005.