AMD Sheds Light on Dual-Core Plans

SAN JOSE, CALIFORNIA -- Advanced Micro Devices' dual-core Opteron processor will fit into the same area occupied by its single-core product, helping to hold down manufacturing costs, AMD said this week at the Fall Processor Forum.

The dual-core Opteron was first demonstrated in a Hewlett-Packard server. It will come with 1MB of Level 2 cache for each core and fit into the same chip sets used by single-core Opteron chips. A chip set connects the processor to a system's memory and I/O ports.

Each dual-core Opteron will consume no more than 95 watts under maximum operating conditions, says Kevin McGrath, an AMD fellow and manager of the Opteron processor architecture. This is slightly more than the 89 watts specified as the maximum power consumption for the current generation of single-core Opteron chips.

The ability to keep the die size constant from single-core chips to dual-core chips was enabled by AMD's 90-nanometer process technology, McGrath says. Chip makers cut their products from fixed-area wafers, so keeping die sizes down is an important consideration in generating the most amount of working chips from a silicon wafer.

Speed Limits

AMD will introduce the dual-core Opterons at lower speed grades than current single-core Opterons, McGrath says. The fastest single-core Opteron in AMD's product lineup runs at 2.4 GHz, and dual-core chips could be expected to run at least 1 GHz slower than similar single-core chips, he says.

Frequency is still an important consideration when determining the overall performance of a system, but dual-core designs allow chip makers to conserve power with slower cores, says Barry Crume, a director with AMD's server and workstation business unit.

In future versions of the Opteron, AMD will adopt multiple core designs and eventually move to multiple memory controllers, McGrath says. One of the reasons behind Opteron's emergence as an item on server shopping lists is its excellent performance on memory-intensive applications. This was enabled by the use of an integrated memory controller on the chip.

As the Sunnyvale, California, company adds multiple cores, it will need additional memory controllers to feed those cores with enough data to ensure the processor is running efficiently, Crume says. Changes in the standard for memory will also require changes to the memory controllers as DDR2 (double data rate) and DDR3 memory evolve over the rest of the decade, he says.

By that time, AMD will also be working on processors for servers with more than eight processors, McGrath says. AMD has only recommended Opteron for servers with eight processors or less up until this point, but the company plans to bring the chip into the "Big Iron" space usually occupied by more expensive servers based on a RISC (reduced instruction set computing) architecture.