Intel Strives for Increased Integration in Future Chips

SANTA CLARA, CALIFORNIA--Intel's vision of a future chip design contains some departures from its current philosophies--moves that are necessary to improve overall system performance as the chipmaker packs more cores onto a single chip.

The new head of Intel's Corporate Technology Group, Justin Rattner, described Intel's evolving vision of what its chips might look like around 2015 in an interview at Intel headquarters Thursday. Intel, like much of the chip industry, has decided that multicore designs are the way to go to improve performance in the future.

But the company will need to change some fundamental aspects of its chip designs by integrating more functionality directly onto the chip, to make sure it provides enough bandwidth for multiple processor cores, Rattner said.

The company is working on an experimental chip design that would integrate a PC or server network controller directly into the cache of a processor, Rattner said. This would accelerate the journey from outside a computer directly into the chip, removing a bottleneck in system performance, he said. Caches store frequently used data in a repository close to the processor, where it can be accessed much faster than data that resides in memory.

Some the early fruits of this project are evident in Intel's I/O Acceleration Technology, announced earlier this year at the Spring Intel Developer Forum, Rattner said. This technology essentially improves the I/O performance of Intel chips by dedicating excess processing resources to I/O functions. It will be available next year with Intel's first dual-core Xeon server chip, code-named Dempsey.

Multicore chips will also need faster connections to memory and graphics chips to improve the overall performance of a system, Rattner said. Intel plans to work integrated memory and graphics controllers into some of its chips over the next ten years, a departure from its current design philosophy, he said.

Get Off the Bus

With the advent of multicore processors, analysts and customers have been urging Intel to move away from its frontside bus design. In Intel's current chips, the interaction between the processor and a system's memory bank is handled by a memory controller on the chip set that feeds data to the processor at various speeds ranging from 400 MHz to 1066 MHz, depending on the chip. This design has served the company well for many years, but as chips start to take advantage of multiple processing units, they require increased amounts of memory bandwidth to perform to their true potential.

Intel rival Advanced Micro Devices implemented an integrated memory controller on its Opteron and Athlon 64 processors to remove this bottleneck, and chip reviewers have commented favorably on the performance of this architecture on memory-intensive applications.

Some aspects of these designs will start to become possible as Intel introduces its 45-nanometer and 32-nanometer processing technologies, which will be capable of producing smaller transistors than Intel's current 90-nanometer processing technology, Rattner said. At the moment, those introductions are scheduled for 2007 and 2009, respectively, on Intel's road map.