• Recommend:
• 0 Comments

More Details Emerge About Intel%squots Next Generation CPU

First version of 64-bit processor will speed by at 900MHz and merges CISC and RISC instructions using Explicit Parallel Instruction Computing.

By Brian McWilliams, PC World News Radio, and Torsten Busse, IDG News Service   

At the Microprocessor Forum going on this week in San Jose, California, Intel and Hewlett-Packard yesterday spelled out some details on the new chip, which is the first to use a new architecture called Explicit Parallel Instruction Computing. The architecture will merge the instruction sets of today%squots Complex Instruction Set Computing and Reduced Instruction Set Computing processors into one processor.

Intel said the first version of the 64-bit Merced processor will likely operate at a clock speed of 900MHz, three times faster than the current top-of-the-line Pentium II. But since it will use parallel techniques, Merced may run even faster.

But don%squott look for Merced chips to show up in desktop PCs anytime soon. Analysts say it will be difficult for Intel to get the yields of the new chip high enough to make it appropriate for anything more than workstations and servers. Some are also skeptical about whether the EPIC architecture will be backward-compatible with current x86 chips and be able to run applications designed to run on that architecture.

Compared to CISC and RISC, EPIC does not follow sequential instruction processing, but rather increases performance by predicting and speculating which functions to process. EPIC reduces the number of branches, or processing paths, and branch mis-predicts to perform at a much higher rate than today%squots CISC and RISC processors, executives from Intel and HP said. Another advantage of the 64-bit architecture is that EPIC technology reduces the effects of memory-to-processor latency.

Intel is also already working on a successor to Merced, which will hit the market around 2001. It%squots expected to have twice the performance of Merced.