Code-named Dunnington, the six-core Xeon processor is designed for servers that have four or more processors. Manufactured using a 45-nanometer production process, the chip should be the last new model based on Intel's Penryn processor design before the release of the company's first Nehalem chips in a few months' time.
Speaking at the Intel Developer Forum in San Francisco this week, Pat Gelsinger, senior vice president and general manager of Intel's Digital Enterprise Group, promised users will see big performance gains from Dunnington.
Unlike quad-core chips used in personal computers, where few applications are designed to tap the power of multi-core processors, commonly used server applications should make full use of the six-core Dunnington chip's power.
"Here, things like virtualization and Web services and cloud computing come into play, and all of these uses have no problem keeping two, four, six or more cores busy," said Dean McCarron, president of Mercury Research, an analyst firm that tracks the microprocessor market.
"This is the area we'll likely see Dunnington make the most impact," he said.
The 45-nanometer production process used to make Dunnington makes possible many of the performance advances over Intel's current chips, which are made using the company's older 65-nanometer process.
"A better process enables higher transistor counts, larger caches and more cores. Ultimately the cores will impact performance more, but the larger caches will help as well," McCarron said.
Dunnington packs significantly more cache than its predecessor. The new chips will have 3M bytes of level 2 cache for each processor core, as well as a shared 16M-byte level 3 cache. By comparison, the Xeon 7300 chips have from 1M byte to 2M bytes of level 2 cache per core, and no level 3 cache.
The larger level 2 cache and addition of a level 3 cache -- already a feature on Advanced Micro Device's quad-core server chips -- allows more data to be stored close to the processor cores, speeding up access to this information and boosting overall performance.
"Going from four to six cores will see close to the 50 percent improvement -- linear scaling -- with a little slowdown due to I/O contention," McCarron said.
The I/O bottleneck in Dunnington stems from the use of older bus technology. Unlike AMD's chips, Intel's server chips use an external memory controller and older bus technology that limits the amount of data that can be pushed through. While the large level 3 cache and 1,066MHz bus speed help minimize this effect, the bottleneck remains and will not be fully addressed until the release of Nehalem server chips for multiprocessor systems next year.
Nehalem, which is also made using a 45-nanometer process technology, incorporates an on-chip memory controller and a new bus technology that should bring a further boost in performance.