Intel takes the chiplet concept to the next level with co-EMIB, ODI connections

We're running out of room on a single chip die. Intel's thinking ahead about how to combine many within a single package.

Intel Lakefield

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Intel’s EMIB was the foundation of the Kaby Lake-G partnership with AMD. Intel’s Foveros stacked-die technology produced the upcoming Lakefield chip. Now Intel is combining EMIB and Foveros into what it’s calling “co-EMIB,” alongside a more advanced ODI interface. 

Both technologies will “improve product-level performance, power and area while enabling a complete rethinking of system architecture,” Intel said in a blog post. Both represent advances in how the chips are packaged and connected, rather than changes in the underlying silicon or the overall microarchitecture.

It isn’t clear when either technology will be introduced to the market, or exactly what products it will influence. We do know, however, what EMIB and Foveros have already produced. EMIB was the foundation for the groundbreaking Kaby Lake-G one-off partnership between AMD and Intel in 2017, and introduced the concept of “chiplets” to the world. Foveros, for its part, is the chip-stacking technology that will be used in the upcoming Lakefield chip, which combines stacked Atom and Core chips for low-power applications. 

Why Intel needs EMIB and Foveros

Why do we need either EMIB or Foveros? Because it’s simply too expensive to cram an entire system’s worth of chips onto a single silicon die. Not only can chips be manufactured more cheaply using a combination of older silicon processes, but manufacturing defects can render that enormous, monolithic die useless. A multitude of smaller, cheaper chips—connected together using high-speed interconnects—can be an effective compromise. EMIB and Foveros help enable that to happen.

The Embedded Multi-die Interconnect Bridge, or EMIB, extends a chip’s I/O pins to the I/O pins of another chip, providing an optimized chip-to-chip interconnect that allows a chip’s package to extend across two dimensions without sacrificing too much performance. It’s also a way for a designer like Intel to save money by fabricating some logic on older, cheaper, technologies, while other cores can be manufactured on its newest, fastest 10nm process. EMIBs can tie them all together.

In 2018, Intel introduced the world to its Foveros stacking technology, which allows chips to extend vertically as well. Foveros helps designers stack a low-power CPU on top of another, and even top it off with memory. Intel said in January that Foveros would be the interconnect that would tie Lakefield together, which it described in more detail in May as a combination between its Sunny Cove and Tremont architectures. 

foveros 3 Intel

 Intel described how the Foveros technology worked late last year.

Co-EMIB, and ODI: Extending chips up, down, and outward

If you’ve understood how the EMIB and Foveros technologies work, you’ll have a better idea of how co-EMIB combines the two. Co-EMIB allows for the horizontal interconnection of two or more Foveros elements with essentially the performance of a single chip, Intel said. It also allows the option to connect memory and even analog logic at high bandwidth and low power. Think of a stacked Foveros chip in the same way a skyscraper stacks floors; the co-EMIB serves as a sort of skybridge between two different Foveros stacks.

skybridge Petronas Ashok Prabhakaran / Flickr

The Intel co-EMIB technology works somewhat like a skybridge between two stacked Foveros towers.

Intel is also talking about what seems to be an optimized version of the Foveros-EMIB combination: the Omni-Directional Interconnect, or ODI. “The top chip can communicate horizontally with other chiplets, similar to EMIB,” according to Intel. “It can also communicate vertically with through-silicon vias (TSVs) in the base die below, similar to Foveros.”

These large vias—metal connections between the different substrate layers—can also allow power to be transferred through to the substrate to whatever logic is on the top die itself, Intel said. Intel made the vias even larger than normal, allowing more power to flow through due to less resistance.

Finally, Intel disclosed what it’s calling MDIO, a new die-to-die interface. In a presentation at Semicon West, Intel said that MDIO will provide 5.4Gbps pin speed when it debuts in 2020.

What this means to you: None of these technologies will directly impact the purchase of your next PC. But they do give Intel even more flexibility in its designs, and provide options for improving performance further by combining logic together in new ways. As Moore’s Law slows (while the demand for continual improvements does not), Intel and its rivals have to think creatively. 

Updated at 11:33 PM with additional details. 

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