Intel continues to talk up its entrance into the discrete graphics market, with its first Xe chips for the PC space planned for 2020. Now the company has revealed a few more details about its plans for the datacenter, as it has announced the “Ponte Vecchio” chip as well.
Ponte Vecchio will be manufactured on Intel’s own 7nm process, a process that’s roughly comparable to where AMD is today. But Ponte Vecchio will probably debut in 2021, rather than next year. Intel didn’t actually confirm those details in its press release, but chief executive Bob Swan had said during Intel’s October earnings call that Intel is “on track to launch our first 7-nanometer based products, a datacenter-focused discrete GPU in 2021.”
In any event, this first Xe chip for the datacenter is also confirmed to use Intel’s stacked-logic Foveros technology, which is being used to manufacture the “Lakefield” chip for dual-display devices. Intel’s leveraging the EMIB chip-to-chip interconnect technology, too, suggesting the Ponte Vecchio chip could be one of the first to use the co-EMIB technology Intel discussed in July.
Ponte Vecchio will be used for HPC modelling and simulation workloads, with the emphasis on AI. It will also tap into the Compute Express Link (CXL), the high-speed accelerator CPU-to-memory and CPU-to-device CXL technology, which maintains memory coherency between the CPU memory space and memory on attached devices. That in turn minimizes resource sharing for higher performance, reduced software stack complexity, and lower overall system cost, according to the CXL Consortium, which includes companies like Google, Microsoft, Intel, Huawei, and HP.
Ponte Vecchio will be programmed using what Intel calls OneAPI, a unified programming API that the company is releasing both as an Intel-specific beta product and an open specification. The idea is that developers would be able to program different Intel chips—Intel Core processors, Intel FPGAs, Xeon, and more—with a single toolset, Intel said.