Intel kicks off a new focus on engineering as it puts the rocky 10nm year behind it
Following a miserable 10nm Cannon Lake launch, Intel signals a strategic shift to focus on six pillars of engineering.
By Gordon Mah Ung
PCWorldDec 12, 2018 6:50 am PST
Image: Gordon Mah Ung
The symbolism surrounding Intel’s Architecture Day briefing—an event to signal a new strategy and own up to past mistakes—couldn’t be richer. The chip giant chose to brief analysts and reporters in Robert Noyce’s house. Noyce, who co-invented the transistor and co-founded Intel in 1968, is said to have held Intel board meetings in the Los Altos home in the early days of the company.
With the company emerging from the fog of a rocky year, it’s here where Intel officials decided to rip off the Band-Aid.
“We have some humble pie to eat,” said Intel’s Chief Engineering Officer, Dr. Murthy Renduchintala when addressing just what went wrong with the company’s 10nm process. “And we’re eating it. But I think that doesn’t in any way, shape, or form diminish my confidence that we have an arsenal of real competitive performance as we look down the next few years,” he said.
Renduchintala was the last to speak after a long day of Intel architects and officials walking the press corps through the company’s ambitious plans.
The highlight of the day was the surprise unveil of the company’s Sunny Cove core design. Also a 10nm CPU, the new Sunny Cove cores are expected next year in laptops first, and appear to pretty much kick the long delayed 10nm Cannon Lake chips overboard with an anchor tied around their necks. For those who need a refresher, Intel couldn’t reach sufficient Cannon Lake yields, and that not only affected the roll-out plans of OEM partners, but also cast doubt on Intel’s engineering.
Indeed, Cannon Lake was originally expected in 2016. but was delayed so many times, customers and the press didn’t even bother to groan the last time Intel delayed it again. Even now, Cannon Lake is barely squeaked out in any reasonable volume.
To prevent a repeat debacle, Renduchintala said Intel plans to decouple its architecture and IP from manufacturing process as much as possible.
“I don’t think there’s any problem in course correction,” Renduchintala said. “I think there is a big problem in being stubborn and being blind to being on the wrong path.”
Illustrating just how Intel has changed, Renduchintala spoke hours after Raja Koduri presented a rethink of Intel’s design and engineering model.
Koduri, a high-profile graphics expert, jumped ship from a resurgent AMD last year for Intel. He explained Intel’s strategic shift would focus on six foundations built around the company’s technology and intellectual property. The six pillars Koduri laid out include:
Process: Described as everything from packaging to its process and fab technology.
Architecture: Includes scalar, vector, matrix, and spatial architectures in CPU, GPU and FPGA.
Memory: Intel’s Optane technology and high-speed storage.
Interconnect: Intel is betting heavily on 5G technology and new interconnect technology that helps it connect disparate types of silicon.
Security: With Intel being plagued by security exploits, Koduri said no longer would security be seen as an afterthought that annoyed architects. Instead, security would have a seat at the table of new designs.
Software: As much as Intel can drive hardware, there’s much more to be gained by optimized software.
Koduri said much of the rethink was based on the epiphany that people are generating data at a faster rate than than tech companies can analyze, transmit, secure and reconstruct in real time.
“What if Peta Flops of Compute and Peta bytes of data are a few single digital milliseconds away from every person on the planet?” Koduri said.
As proof of what Intel expects on the horizon, the company showed off a new 3D stacking technology called “Foveros.” As the next step beyond its EMIB technology, which Intel uses to join different chips together, Foveros allows Intel to, say, stack a low-power CPU on top of a high-power CPU, and then top it off with RAM.
If a device doesn’t need the horsepower of the high-power CPU, the low-power core is used. If this sounds like ARM’s “big.LITTLE” approach, it should. Intel’s approach, however, could one day approach the performance of what it squeezes out of its monolithic dies—but with silicon Lego’ed together to make the whole product cheaper.
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