Intel: Keeping up with Moore’s Law is becoming a challenge
By Agam Shah
Intel will advance Moore’s Law for the foreseeable future, but keeping up with it is becoming more challenging as chip geometries shrink, according to a company executive.
Moore’s Law is based on a theory that the number of transistors that can be placed on silicon doubles every two years, which brings more features on chips and provides speed boosts. Using Moore’s Law as a baseline, Intel for decades has added more transistors while reducing the size and cost of a chip. The manufacturing advances help make smartphones, tablets and PCs faster and more power efficient.
But as chips get smaller, maintaining pace with Moore’s Law is perhaps more difficult today than it was in years past, said William Holt, executive vice president and general manager of Intel’s Technology Manufacturing Group, during a speech at the Jeffries Global Technology, Media, and Telecom Conference this week.
“Are we closer to an end than we were five years ago? Of course. But are we to the point where we can realistically predict that end, we don’t think so. We are confident that we are going to continue to provide the basic building blocks that allow improvements in electronic devices,” Holt said.
The end of the industry’s ability to scale chips down in size has “been a topic on everybody’s mind for decades,” Holt said, but dismissed arguments by observers and industry executives that Moore’s Law was dead. Some predictions about the law were short-sighted, and the paradigm will continue to apply as Intel scales down chip sizes, Holt said.
“I’m not here to tell you that I know what’s going to happen 10 years from now. This is much too complicated a space. At least for the next few generations we are confident we don’t see the end coming,” Holt said, talking about generations of manufacturing processes.
Moore’s Law was first established in 1965 by Gordon Moore, who co-founded Intel in 1968 and ultimately became CEO in 1975. The original paper on the law, published in Electronics magazine in 1965, focused on the economics related to cost-per-transistor, which would come down with scaling.
“The fact that now as we look at the future, the economics of Moore’s Law … are under considerable stress is probably appropriate because that is fundamentally what you are delivering. You are delivering a cost benefit each generation,” Holt said.
But Holt said that manufacturing smaller chips with more features becomes a challenge as chips could be more sensitive to a “wider class of defects.” The sensitivities and minor variations increase, and a lot of attention to detail is required.
“As we make things smaller, the effort that it takes to make them actually work is increasingly difficult,” Holt said. “There are just more steps and each one of those steps needs additional effort to optimize.”
To compensate for the challenges in scaling, Intel has relied on new tools and innovations.
“What has become the solution to this is innovation. Not just simple scaling as it was the first 20 years or so, but each time now you go through a new generation, you have to do something or add something to enable that scaling or that improvement to go on,” Holt said.
Intel has the most advanced manufacturing technology in the industry today, and was the first to implement many new factories. Intel added strained silicon on the 90-nanometer and 65-nanometer processes, which improved transistor performance, and then added gate-oxide material—also called high-k metal gate—on the 45-nm and 32-nm processes.
Intel changed transistor structure into 3D form on the 22-nm process to continue shrinking chips. The latest 22-nm chips have transistors placed on top of each other, giving it a 3D design, rather than next to each other, which was the case in previous manufacturing technologies.
Intel in the past has made chips for itself, but in the last two years has opened up its manufacturing facilities to make chips on a limited basis for companies like Altera, Achronix, Tabula and Netronome. Last week Intel appointed former manufacturing chief Brian Krzanich to CEO, sending a signal that it may try to monetize its factories by taking on larger chip-making contracts. Apple’s name has been floated around as one of Intel’s possible customers.
For Intel, the advances in manufacturing also correlate to the company’s market needs. With the PC market weakening, Intel has made the release of power-efficient Atom chips for tablets and smartphones based on the newest manufacturing technologies a priority. Intel is expected to start shipping Atom chips made using the 22-nm process later this year, followed up by chips made using the 14-nm process next year.
Intel this week said upcoming 22-nanometer Atom chips based on a new architecture called Silvermont will be up to three times faster and five times more power-efficient than predecessors made using the older 32-nm process. The Atom chips include Bay Trail, which will be used in tablets later this year; Avoton for servers; and Merrifield, due next year, for smartphones. Intel is trying to catch up with ARM, whose processors are used in most smartphones and tablets today.
The process of scaling down chip sizes will require lots of ideas, many of which are taking shape in university research being funded by chip makers and semiconductor industry associations, Holt said. Some of the ideas revolve around new transistor structures and also materials to replace traditional silicon.
“Strain is one example that we did in the past, but using germanium instead of silicon is certainly a possibility that is being researched. Even more exotically, going to III-V material provide advantages,” Holt said. “And then there are new devices that are being evaluated as well as different forms of integration.”
The family of III-V materials includes gallium arsenide.
The U.S. government’s National Science Foundation is leading an effort called “Science and Engineering behind Moore’s Law” and is funding research on manufacturing, nanotechnology, multicore chips and emerging technologies like quantum computing.
Sometimes, not making immediate changes is a good idea, Holt said, pointing to Intel’s 1999 transition to the copper interconnect on the 180-nm process. Intel was a late mover to copper, which Holt said was the right decision at the time.
“That equipment set wasn’t mature enough at that point in time. People that moved [early] struggled mightily,” Holt said, adding that Intel also made a late move to immersion lithography, which saved the company millions of U.S. dollars.
By the time Intel moved to immersion lithography the transition was smooth, while the early adopters struggled.
The next big move for chip manufacturers is to 450-mm wafers, which will allow more chips to be made in factories at less cost. Intel in July last year invested $2.1 billion in ASML, a tools maker, to enable smaller chip circuits and larger wafers. Following Intel’s lead, TSMC (Taiwan Semiconductor Manufacturing Co.) and Samsung also invested in ASML. Some of TSMC’s customers include Qualcomm and Nvidia, which design chips based on ARM processors.
Intel’s investment in ASML was also tied to the development of tools for implementation of EUV (extreme ultraviolet) technology, which enables more transistors to be crammed on silicon. EUV shortens the wavelength range required to transfer circuit patterns on silicon using masks. That allows creation of finer images on wafers, and chips can carry more transistors. The technology is seen as critical to the continuance of Moore’s Law.
Holt could not predict when Intel would move to 450-millimeter wafers, and hoped it would come by the end of the decade. EUV has proved challenging, he said, adding that there are engineering problems to work through before it is implemented.
Nevertheless, Holt was confident about Intel’s ability to scale down and to remain ahead of rivals like TSMC and GlobalFoundries, which are trying to catch up on manufacturing with the implementation of 3D transistors in their 16-nm and 14-nm processes, respectively, next year. But Intel is advancing to the second generation of 3D transistors and unlike its rivals, also shrinking the transistor, which will give it a manufacturing advantage.
Speaking about Intel’s rivals, Holt said, “Since they have been fairly honest and open they are going to pause area scaling, they won’t be experiencing cost saving. We will continue to have a substantial edge in transistor performance.”