Intel is drumming up support for its latest 50-core Knights Corner and Xeon E5 server chips, which are key elements in the company’s plans to scale performance while reducing power consumption moving toward an exascale supercomputer by 2018.
Intel showed for the first time at the SC11 supercomputing conference a chip code-named Knights Corner, which has more than 50 cores designed to handle high-performance computing workloads. The conference runs through Friday in Seattle.
Intel also talked about its upcoming Xeon E5 server chips, which are based on the Sandy Bridge microarchitecture. One processor in the E5 family, the E5-2600, delivers double the performance compared to the Xeon 5600 server chip based on Intel’s prior Westmere architecture, said Joe Curley, director of marketing in the technical computing group at Intel.
Both of the chips are being paired in a supercomputer called Stampede, which will be deployed in 2013 at the Texas Advanced Computing Center at the University of Texas. The supercomputer will deliver peak performance of 10 petaflops (or 10,000 trillion operations per second). The E5 processors will assume 20 percent of the supercomputer’s performance, while Knights Corner will handle 80 percent, or around 8 petaflops.
Today’s fastest supercomputer is K Computer at the Riken Advanced Institute for Computational Science in Japan, which reaches about 10 petaflops in performance, according to the Top500 list of fastest supercomputers in the world issued on Monday.
The Knights Corner chip mixes standard x86 CPU cores with specialized cores and works as an accelerator alongside the CPU to boost parallel application performance. The Knights Corner chip is an important component in Intel’s aim to reach exascale computing by 2018, Curley said.
Exascale computing is a key landmark in the computing space to enable new medicine, defense, energy and science applications. Countries such as Japan, China and the U.S. are in a race to get to exaflop computing and beyond.
However, design constraints and high power consumption have limited the development of an exaflop supercomputer. Chip makers like Intel, Nvidia and Advanced Micro Devices are developing accelerators to work alongside the CPU to boost supercomputing performance while reducing power consumption. Of the top 500 supercomputers, 39 systems used graphics processors as accelerators, including second-ranked China’s Tianhe-1A, which delivers 2.57 petaflops of peak performance.
Intel’s Knights Corner chip, part of an architecture called MIC (many integrated cores), plugs into the PCI-Express slot and is considered an accelerator in the vein of graphics processors. However, Knights Corner’s fundamental architecture is different and Curley said it offers a competitive advantage because it works better with existing x86 code.
“What we’ve always said with MIC is breakthrough parallel performance … in a general-purpose CPU architecture, but you get greater reuse of code,” Curley said. “If you change the entire programming model the machine becomes difficult to use.”
Nvidia, however, said it is easy to accelerate GPUs using directives, which are “hints” that programmers provide to the compiler to identify areas of code to accelerate, a company spokesman said. The compiler does the work of mapping the computation on to the accelerator, in the process eliminating the need for programmers to modify or adapt underlying code. Nvidia this week announced OpenACC, an open industry standard for directives-based programming, which is backed by companies including supercomputer maker Cray.
But Intel’s Curley said the programming principals for MIC architecture are around open standards and high-level abstract programming. The company is making investments in software programming tools so that the code maps well to parallelism.
Intel also said its Knights Corner chip is the first single chip to achieve 1 teraflop of double-precision performance, which will provide more accurate results on technical, scientific and mathematical calculations.
“It’s a major breakthrough in performance,” Curley said.
Intel also used SC11 to push its new Xeon E5 server chip, which is being used in 10 of the Top500 supercomputers, the company said. The E5 chips are the fastest-ramping server chips in Intel’s history, and the company has 400 design wins around the processor, Curley said.
The chip enables many new technologies to boost server performance. The chip is the first to integrate support for PCI-Express 3.0, which will boost on-board bandwidth to scale server performance. The bus standard can transfer data at speeds of 8 gigatransfers per second, a 60 percent improvement over PCI-Express 2.0, which is currently found in servers.
Silicon Graphics said it would include E5 chips in its upcoming blade servers based on the ICE X architecture. The blade is based on a rack-level design and can scale to hundreds of server nodes for high-performance computing. SGI’s ICE servers will start shipping later this quarter. Supermicro also showed the X9 server motherboards for eight-core E5 processors.
Servers with E5 chips will be widely available in the first half of next year, an Intel spokesman said.
The E5 chip will compete with Advanced Micro Devices’ Opteron 6200 chip, which includes up to 16 cores. AMD’s chip was announced earlier this week.