Did you miss yesterday’s Intel Developer Forum announcements? Catch up in our day one recap–and read our previous IDF coverage here.
Much of the Intel Developer Forum’s first day was spent talking about Ivy Bridge, Intel’s next generation CPU built on the upcoming 22nm tri-gate process technology. Normally, Ivy Bridge would be the “tick” in Intel’s “tick-tock” model of processor product development. The “tick” refers to moving to a new, higher density process technology. When Intel does that, the first CPU product it builds on the new manufacturing process, is usually a tweaked and enhanced version of an existing CPU architecture. The “tock” is when Intel, now comfortable with a new process, designs a new architecture, then builds it on the now familiar process.
On the x86 CPU side, Intel pretty much did just that with Ivy Bridge. There will be some performance improvements over the existing Sandy Bridge architecture, but those will be incremental. Power efficiency is likely to be substantially better, however.
Much of the emphasis on Ivy Bridge is in power efficiency. The CPU will enable DDR I/O power gating, configurable TDP (thermal design power) and power-aware interrupt pairing. Configurable TDP is interesting in that current Intel CPUs offer a single thermal design power point. Configurable TDP will allow system makers to design a single CPU into a variety of form factors, including cases that may offer limited cooling, without sacrificing base level performance. In addition, Ivy Bridge will support DDR3L, the new low voltage DDR3 standard running at 1.35v.
Intel is improving overclocking capabilities, increasing the maximum multiplier ratio support from 57 to 63. Another interesting change is dynamic overclocking, letting users change clock speed through software without rebooting the system.
Intel also added a new digital random number generator that’s supposedly much more robust and and much speedier than current methods. Also added is Supervisor Mode Execution Protection, a hardware technique to prevent malware from jumping across hardware security levels inside the CPU.
The designers also added an L3 cache to the GPU itself. In addition to performance improvements, the cache also helps power efficiency, since anything located in the cache means the CPU ring bus doesn’t need to be fired up. Execution units have been enhanced, most importantly by extending the co-issue of operations to many more instructions than Sandy Bridge’s graphics core was capable of.
Overall, Piazza estimates double the overall throughput of the core, compared to Sandy Bridge GPUs, but some areas may see even greater performance increases, while achieving the goal of greater power efficiency. Will an integrated GPU from Intel finally get some respect from gamers? Only time will tell.
Ivy Bridge products are slated to ship sometime in the first half of 2012, but further details on product models and clock speeds aren’t known.
The Intel Showcase and the X79 Factor
Intel always has a trade show in miniature at IDF, mostly highlighting partner products using Intel technology. While Ivy Bridge is interesting, it’s a few months out. Most of the actual product attention is on Sandy Bridge Extreme, which will be a new high end CPU from Intel replacing the current Gulftown six core processors, like the Core i7 990X. Sandy Bridge Extreme will ship late in 2011.
Sandy Bridge Extreme, often abbreviated SBe, will require a new chipset and socket. The socket, dubbed LGA2011, will replace the aging LGA1366. The chipset is the X79 chipset. SBe and the chipset together will support four channels of DDR3 memory. Let’s look at a few X79 boards.
Stay tuned for more Intel Developer Forum coverage.