Taiwan Semiconductor Manufacturing Co. is vying with Intel to become the first company to sell three-dimensional chips that boost the density of transistors in a single semiconductor by up to 1000 times.
TSMC, the world’s largest contract chipmaker, could make its first 3D chips commercially available before the end of 2011, according to a person close to the situation who requested anonymity.
The timeframe for TSMC matches the end-2011 schedule that Intel has set for the launch of its 3D Tri-Gate chips, which the company expects to be the world’s first commercial 3D chip and the most significant advance in chip technology since the development of the chip transistor in the 1950s.
With several layers of silicon stacked together, a 3D chip can achieve performance gains of about a third while consuming 50 percent less power. For this reason, 3D chips are particularly well suited to power new generations of mobile devices such as tablets and mobile phones, businesses where Intel has so far failed to establish a significant presence.
“This is definitely a new business opportunity for TSMC,” said Shang-Yi Chiang, senior vice president for R&D at TSMC, in an interview. “We are building a patent portfolio now.”
3D chips are expected to solve a number of problems for chipmakers who are aiming for performance increases in ever-smaller chips. As transistor density rises, the wires connecting them have become both thinner and closer together, resulting in increased resistance and overheating. These problems cause signal delays, limiting the clock speed of central processing units.
“3D chips look more attractive because of their greater density,” Chiang said. “However, it is more difficult to make them because of the testing issues. If you have five stacked dies and one of the dies is bad, you have to scrap the whole thing.”
For this reason, TSMC is also developing so-called 2D chips that replace an organic polymer substrate with silicon to boost transistor density. Communications chipmaker Xilinx has contracted TSMC to make its Virtex-7 field programmable gate array (FPGA) using TSMC’s 2D chip technology that puts three chip dies on one silicon substrate. Xilinx said on March 8 that it expects the first samples of the Virtex-7 485T FPGA to be available by August.
TSMC’s Chiang said the company has been working closely with chip packagers and providers of design automation software to help commercialize 3D chip technology.
In April 2007, IBM and Rensselaer Polytechnic Institute (RPI) researchers announced the first versions of 3D chips with support from the Defense Advanced Research Project Agency (DARPA). The 3D chips combined several layers of silicon using a technique called wafer bonding.
IBM’s technique used a silicon base with active wafers layered on top. This technology allowed a processor to be placed on the bottom of the stack with memory or other components layered across the top, resulting in a thousand-fold reduction in connector length. The greater transistor density reduced the distance data has to travel, resulting in much faster processing.
IBM used through-silicon vias (TSVs) to connect stacks of multiple chip components. TSVs allow for more efficient heat dissipation through the stack to cooling systems that improve power efficiency.