To use multicore processors effectively the technology industry needs to radically rethink the basic computer architecture it has used over the past 50 years, a University of Maryland researcher argues in the January edition of the Association for Computing Machinery’s flagship Communications publication.
“The recent dramatic shift from single-processor computer systems to many-processor parallel ones requires reinventing much of computer science to build and program the new systems,” argues Uzi Vishkin, a professor at the University of Maryland Institute for Advanced Computer Studies, in the paper.
Vishkin even offers a new architecture abstraction, which he calls ICE (Immediate Concurrent Execution), and which he developed with funding from the U.S. National Science Foundation.
The basic computer architecture we use today is based on the concepts put forth by mathematician John von Neumann in the 1940s. In his architecture, data and programs are held in computer memory and fed to the computer’s CPU. Programs are executed using a program counter, which supplies the CPU the address of the next instruction in memory to execute.
This approach allows what Vishkin calls serial computing, a design in which “any single instruction available for execution in a serial program executes immediately.”
But it is limited because it allows only a single instruction to be executed at a time. In an age of multicore processors and large amounts of available memory, this limit is no longer necessary, Vishkin argues. Instead, multiple instructions can often be executed much faster in parallel — all at the same time and in a single step.
Vishkin’s alternative varies the von Neumann architecture by allowing an indefinite number of instructions to be executed at any given time, which could greatly simplify matters for programmers. With ICE, “You could dream up any number of instructions as long as the input for one is not the output for the another,” he said. The programmer wouldn’t have to worry about how many processors would be available for the task.
Such an architecture, Vishkin states, would require changes in hardware design. For the approach to operate, the chips would require a high-bandwidth, low-latency network between the processors and memory. The hardware would have a single processor core to control all the other cores. If the code is serial, it can be executed on that core. If there are additional instructions, the central processor can dole out additional instructions to the other cores.
Vishkin has six patents on the technology and the research team built prototype hardware to run on the ICE abstraction.
Joab Jackson covers enterprise software and general technology breaking news for The IDG News Service. Follow Joab on Twitter at @Joab_Jackson. Joab’s e-mail address is Joab_Jackson@idg.com
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