Intel will release its fastest and highly anticipated eight-core Nehalem-EX server processor later this month, a company executive said late Thursday.
The processor will be targeted at four-socket servers, said Shannon Poulin, Xeon platform director at Intel. Each physical core will be able to run two threads simultaneously, giving the chip 64 virtual processing cores on servers.
Intel’s CEO Paul Otellini has described Nehalem-EX as Intel’s fastest processor to date. The chip maker announced the processor last year, and said it would release the chip in the first half of this year, but did not provide an exact release date.
Poulin declined to provide the clock speed of the chips. However, the company has said it will include 24MB of cache, and 2.3 billion transistors.
Intel is targeting the chip at high-end systems running data-intensive applications such as databases. IBM earlier this week said it would implement Nehalem-EX chips in its System x EX5 servers.
The chip will be made using the 45-nanometer process, and be based on the Nehalem microarchitecture, which integrates the memory controller and improves system speed by cutting data bottlenecks that plagued Intel’s earlier chips.
Intel is also including new technologies like MCA recovery error correction that could make servers more fault tolerant and provide greater uptime, he said. The processor will be able to detect system errors originating in the CPU or system memory and correct them by working with the operating system. Some of these technologies have been adapted from Intel’s high-end Itanium processors, which are based on a separate chip architecture and go into fault-tolerant systems.
The new processor will also contain separate buffered memory chips that can store data temporarily alongside the main memory for faster task execution.
Intel will also offer four memory channels per processor, Poulin said. That will put it on par with Advanced Micro Devices’ twelve-core Opteron server processors, code-named Magny-Cours, which also offer four memory channels per processor. More channels provide more memory bandwidth to run programs faster.
AMD has started shipping Magny-Cours processors, and Intel’s Nehalem-EX should intensify the battle between the rivals as both companies reach out to claim benchmark crowns, said Nathan Brookwood, principal analyst at Insight 64. Intel will build large amounts of cache inside Nehalem-EX that could help the processor deliver faster performance, but AMD’s Magny Cours has more physical cores per chip.
Benchmark results could vary depending on the type of task assigned, but performance is just one part of the story, Brookwood said. Nehalem-EX could reach out to new markets with additional features like fault-tolerance, Brookwood said. It could tread into territory of high-end servers dominated by Intel’s Itanium and chips based on RISC (reduced instruction set computer) architecture, which includes IBM’s Power and Sun’s Sparc processors.
But AMD could hold an advantage over Intel’s Nehalem-EX in pricing. Intel could charge a premium for Nehalem-EX chips, while AMD chips could deliver better bang-for-buck per core with Magny-Cours, Brookwood said.
Intel’s Poulin also said the company would release its next-generation Xeon server processors based on the Westmere microarchitecture later this month. The processors will be targeted at two-socket servers, Poulin said. Chips for four-socket servers will be released next year.
Intel has said that server chips based on Westmere will contain up to six cores. The company last month said the six-core chip contained 1.17 billion transistors and 12MB of cache. The six-core chips will deliver improved performance and power savings compared to earlier quad-core chips, according to Intel.
The Westmere-EP chips will fall under the Xeon product line and will be made using the 32-nanometer process. The last refresh for server chips was in March last year, when the company announced a range of Xeon 5500 series and 3500 series chips based on the Nehalem architecture. The chips were made using the 45-nm process.